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Learning Session

Wednesday, 5/21

3:00 PM
SEU System Analysis: Not Just the Sum of All Parts

Melanie D. Berg
ASRC Federal Space and Defense

This talk will provide a top level description of interpreting SEU test
data on the system level taking into account actual circuit operations
and not simply SEU charge generation


4:00 PM
Fault Tolerant Techniques for Embedded Processors in FPGAs

Fernanda Lima Kastensmidt
UFRGS, Instituto de Informática, Porto Alegre, Brazil

Soft and hard-core processors are present in many FPGAs. Soft errors can
affect the correct execution of a program provoking data and
control flow errors which in high-reliability systems require mitigation.
These fault tolerant techniques can be based on hardware redundancy,
software-based and a combination of both. This learning session
will present some of the major fault tolerant techniques,
some recent radiation results and new trends


Contact Us

General Chair(s): Robert Weller, Vanderbilt University (SEE) / Tim Gallagher, Lockheed Martin (MAPLD)
Technical Program Chair(s): Ethan Cannon, Boeing (SEE) / Gabe Mounce, USAF and Michael Coe, SEAKR (MAPLD)
Poster Session Chair(s): Nathaniel Dodds, Sandia and Martha O'Bryan, AS and D, Inc. / GSFC
Publications Chair(s): Mike Wirthlin, BYU and Steven Buchner, NRL
Industrial Exhibit Chairwoman: Teresa Farris, Aeroflex Corp.
Treasurer: Bill Lotshaw, The Aerospace Corporation
Local Arrangements & Registration Services: Susan Hunt, STAMP Services
Website Curator: Carl Szabo, AS and D, Inc. / GSFC

SEE Symposium and MAPLD are supported by the Aeroflex Corporation, the Aerospace Corporation, Brigham Young University, Lockheed Martin, the NASA Electronic Parts and Packaging Program, the Naval Research Laboratory, Sandia National Laboratories, and Vanderbilt University.