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To submit an abstract to SEE/MAPLD, please fill out the fields below

Guidelines for Submissions:
Abstract submissions are a minimum of 2 and a maximum of 4 pages
File format is MS Word .docx or Adobe PDF format

Here is our abstract template (.docx)

Abstract Submission Due Date: Friday, March 15th, 2019

After the submission due date, the workshop committee will contact all authors by email
to indicate whether their presentation(s) have been accepted or declined

Abstract Title:
First Name:
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Completed Abstract File:
*Select an appropriate session for your abstract:
(Refer to the table below)
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SEE / MAPLD Sessions
SEE Symposium MAPLD
Phenomena: Upset, Transients, Latchup, Gate Rupture, Burnout, Destructive Effects in Bipolar Devices. FPGAs, PLD and New Devices: New and/or novel FPGA, PLDs; Benchmarking of FPGAs, PLDs; Applications of spaceborne processing.
Basic Mechanisms and Modeling: Destructive and Non-Destructive Effects, Nanoscale Phenomena, Effect of Operating Speed, Charge Transport and Collection, Impact of Circuit and Environmental Parameters. Mitigation of Single event effects in PLDs, FPGAs, and commercial electronics: Multi-level approaches for high reliability and fault tolerance (redundancy, TMR, SET filtering, etc…), SEU mitigation techniques and SEE automated tools.
SEE Mitigation Methods Including Hardened by Design (HBD) and by Process: Approaches for gaining SEE hardness in commercial devices. Designing with FPGAs and PLDs: Agile methods, ESL/HLS and Model Based Engineering development techniques, embedded processing, and speeding up synthesis and PAR (NSF CHREC).
Environments and Facilities: Space, Atmospheric and Terrestrial environments. Heavy Ion, Proton, Neutron and Laser Test Facilities. Validation and Verification of FPGAs and PLDs: Verification techniques and languages such as co-simulation, System Verilog and OVM/UVM. Simulation speed-up techniques, emulation, new tools and methods for design validation.
Operational Regimes and Performance Data: Systems and Devices at LEO to Geosynchronous and Beyond, High Altitude Aircraft, and Terrestrial. Reliability/Availability/Susceptibility of programmable devices: Failure mechanisms, reliability testing and characterization, packaging reliability, reliable design practices.
Electronic & Photonic Device Data, Techniques, and Diagnostics: Memories, Latches, Analog Circuits, Microprocessors, FPGAs, Optocouplers, DC to DC Converters, Sensors, Commercial and Hardened Components, Data Capture Methods, and Data Analysis. Novel Applications and Case Studies: Reconfigurable computing, high-performance processing using programmable logic, successful deployment of programmable logic, novel applications and design studies.
Systems: Error Mitigation, Error Detection & Correction, Multi-core Processing, and Fault Tolerant Systems. Education: Education practices, market demands for military and aerospace component engineers, and engineer retention.
Event Rate Computation: Analytic, Monte Carlo, Mixed-Level (Radiation Transport + SPICE, TCAD + SPICE, etc.) Technical Management of FPGAs and PLDs: Technical leadership, process management and metrics.
Poster Session (SEE and MAPLD)
Material relevant to any of the above, both SEE and MAPLD, may be presented as a Poster
*All options subject to change any time, per the discretion of the conference committee

Industrial Exhibit Chairwoman: Teresa Farris, Cobham Semiconductor Solutions
Local Arrangements & Registration Services: Susan Hunt, STAMP Services
Website Curator: Carl Szabo, AS and D, Inc. / GSFC

SEE Symposium and MAPLD are supported by Cobham Semiconductor Solutions, the Aerospace Corporation, Brigham Young University, Lockheed Martin, the NASA Electronic Parts and Packaging Program, the Naval Research Laboratory, Sandia National Laboratories, and Vanderbilt University.