The Air Force/Phillips Laboratory contracted to develop radiation-hardened Field Programmable Gate Arrays (FPGAs). This note will describe some of the technical aspects of this development and current results.

DEVICES: The RH1020 and the RH1280 are radiation hardened versions of the A1020B (1.0 um) and the A1280XL (0.8 um) and are functionally compatible. Principally, the A1020B has improved clock skew performance over its predecessors. Here is a brief list of differences for the A1020B: (1) Increased drive and speed for the clock network by use of an independent, enlarged, TTL translator at pad; (2) high- efficiency buffers for the clock tree; (3) row drivers for clock shorted together behind the isolation device for current sharing; and (4) widening of the isolation device which lowers series resistance at the top of the clock tree for smaller propagation delays and reduced skew. The A1280XL differs from it's predecessors (such as the A1280A) as follows: (1) I/O modules redesigned to improve pin-to-pin and clock-to-output delays; (2) enhanced clock trees to minimize clock delays and skew; (3) different characteristics for SDI and DCLK when unused [see last quarters notes]; and (4) the A1280XL has a slightly different specification for the programmer/debugger, with three more bits in the command shift register than the A1280A.

SPECIFICATION: The RH1280 will be added to 5962-90156 (submittal end of February) and the RH1020 will be added to 5962-90965 (submittal end of Q2).

FOUNDRY AND PROCESS: All manufacturing operations including device fabrication, assembly, and test will be done at Loral with parts built on their radiation-hardened epitaxial bulk RHCMOS process (0.8 um). The base layers are standard Loral process with high voltage transistors and ONO antifuses Actel designs. The thickness of the antifuse has been increased to prevent Single Event Dielectric Rupture (SEDR), a partial programming of an antifuse by a heavy ion. Nominal Actel antifuse thickness is ~ 86Å (oxide-equivalent) and the RH1280 lot currently in qualification is using a 99Å thick antifuse. Use of the Loral plug technology ensures no step coverage issues with these parts. The parts will be run on a 5V line; 3.3V parts, if available, will be a characterized version of the 5V parts as there is no plan to move to the 3V line.

PACKAGES: Standard packages will be the QFP172 for the RH1280 and the QFP84 for the RH1020. PGAs will be a special order. All lids will be grounded (current Actel products have floating lids).

TIMING PERFORMANCE: For the RH1280, a pre-radiation timing model is available for Designer 3.0 by installing the 3.0.1s silicon update and post-300 krad model will be available in Designer 3.1 No estimate for performance of the RH1020 has been received

PROGRAMMING: Programming will be supported on the Activator 2 and the Activator 2S starting with Designer 3.1. Data I/O programmers will not be supported for either of the devices. Programming yield is expected to equal that of standard Actel devices and Actel's return policy for devices that do not program will be maintained. Because of the increased thickness of the antifuse, programming time per device will substantially increase, with current patterns taking approximately 50 minutes per device.

RADIATION PERFORMANCE (RH1280):

TOTAL DOSE:

Approximate 10% increase in tpd @ 300 krads. Icc information not yet available. Gross functional failure started to occur at 500 krads, with VCC = 4.5 VDC.

SEU:

Single Event Upset performance of C- and S- modules shows similar results to the A1280A. This extends to error rates and the sensitivity to logic state. SEU performance of the I/O latches has not yet been measured and will be tested in the near term.

SEDR:

With the increase of antifuse thickness, it is expected that no Single Event Dielectric Rupture (antifuse partial programming by a heavy ion) will occur. Test results to date have detected no SEDR.

LATCHUP:

The devices are expected to be latchup immune. Tests showed no latchup at an LET of 180 MeV-cm2/mg at VCC = 5.5 VDC at a temperature of 125°C.

DOSE RATE UPSET:

> 1 x 109 rad(Si)/sec (target).

SURVIVABILITY:

> 1 x 1012 rad(Si)/sec (target)

NEUTRON FLUENCE:

> 1 x 1014 N/cm2 (target)

SEE PERFORMANCE OF ACTEL FPGAs

Flight applications of FPGAs are increasing with more designers starting to utilize these devices. Additionally, high level design tools, such as macro generators, optimizers, and hardware description languages provide a level of abstraction to the designer. However, to ensure successful on-orbit performance and meet mission requirements, it is necessary to understand the underlying implementation and the radiation effects. Recently, an application with significant SEU requirements (LET threshold of 37) was designed using high-level tools, with the designer unaware of the Actel FPGA architecture and implementation dependent radiation susceptibilities which resulted in later design modifications (unpleasant at that stage of the project). This tip shall review storage elements in the Actel FPGAs and SEE data for each of the products and structures and the implications of using advanced tools.

There are currently 4 basic families of Actel FPGAs: Act 1, Act 2 (and A1200XL), Act 3, and the 3200DX. The Act 1 devices are composed entirely of C-Modules (or combinational modules) and I/O modules. Both of these modules are purely combinational and have no storage capability. Flip-flops are made by configuring a single C-Module as a transparent latch or by using two C-Modules as an edge-triggered flip- flop. The Act 2 family added the S-Module (essentially a C- Module followed by a dedicated flip-flop) and transparent latches to the input and output paths in the I/O modules. The S-Module flip-flop may be configured as either an edge- triggered device or a transparent latch. The Act 3 series replaced transparent latches in the I/O modules with edge- triggered flip-flops driven by a high performance clock that guarantees a th of 0 nS for input flip-flops. For storage, the 3200DX family adds internal dual-port SRAM to the Act 2 resources. To date, the A1020x (Act 1) and the A1280x have been subject to significant SEE studies. The A1460A (Act 3) and the RH1280 have been subject to initial tests, with the A12xxXL and the RH1020 planned for testing in the near future. Planning has started for testing the A32200DX (20,000 gate array, internal SRAM, and JTAG). The following table summarizes SEE performance (and will be updated as new results come in):

Device          Feature  SEU     Sat       Temp
                Size     LETth   X-section
---------------------------------------------------
A1010           2.0      25      5x10-6    R-->100C
A1020           2.0      25      5x10-6    R-->100C
A1020A          1.2      25      3x10-6    R
A1280 C         1.2      23      3x10-6    R-->100C
A1280 S         1.2       5      8x10-6    R-->100C
A1020B          1.0      28      2x10-6    R
A1280A C        1.0      28      2x10-6    R
A1280A S        1.0       5      8x10-6    R
A1280A I/O In   1.0			
A1280A I/O Out  1.0      28		
A1280A 3.6V     1.0                        R
RH1280 C        0.8      22      8x10-6    R-->125C
RH1280 S        0.8       3      9x10-6    R-->125C
RH1280 I/O In   0.8	 		
RH1280 I/O Out  0.8			
A1460A C        0.8              ~2x10-7   R
A1460A S        0.8      >6      1x10-6    R
A1460A I/O      0.8			
A1460A C 3.3V   0.8     ~25      8x10-7    R
A1460A S 3.3V   0.8      <6      2x10-6    R
A1460A I/O 3.3  0.8

Device          Feature  SEL     SEDR   Clock Upset
                Size
---------------------------------------------------
A1010           2.0      NO		
A1020           2.0      NO      YES    Observed
A1020A          1.2      NO      YES	
A1020B          1.0      YES*    YES	
A1280           1.2      NO      YES	
A1280A          1.0      YES+    YES	
A1280A 3.6VDC   1.0      NO      NO	
RH1280          0.8      NO      NO	
A1460A          0.8      NO      YES	

Notes:

1. A1460A Results same for routed global clocks and HCLK.
2. * Latchup for A1020B detected at LET = 55 MeV/(mg/cm2)
3. + Latchup detected only with MODE pin high.
3. Single cell, C-Module latches have not yet been tested. A1020B tests planned in near term.
4. Blank cells denote either 'not measured' or 'not yet observed.'
5. Cross-sections are in cm2/flip-flop

The obvious conclusions are:

1. Flip-flops made from two C-modules are relatively hard.
2. Flip-flops made from a single S-Module is relatively soft.
3. TMR techniques are required to make flip-flops very hard ( < 10-10 errors/bit-day)
4. A1020B devices are the only devices known to latch up.
5. All devices tested, with the exception of the RH1280 (preliminary tests), have shown susceptibility to SEDR. This is expected, since all of the devices share a common antifuse design. Running at 3.6 VDC lowers the bias across the antifuse and no SEDR was observed under these conditions.
6. RH1280 devices offer no significant improvement in SEU performance for C- and S-Modules.
7. 3.3 volt operation eliminates SEDR from Actels and increases SEU rate.

PROGRAMMING TIPS

1. When using Windows for Workgroups 3.11, it is recommended that the network connection be removed prior to programming devices. It has been noted that certain network disruptions can cause the PC to hang.

2. Uninterruptible Power Supplies (UPS) should be used when programming RH1280 devices. This is recommended based on the increased programming time and high cost of the devices.

3. For users programming Act 1 devices in the ALS 2.3.1 or 2.3.2 systems, there is a bug in the programming algorithm which may result in incorrectly programmed devices. There is a patch available to fix this bug.

4. On Act 3 devices, the HCLK and IOCLK nets cannot be internally probed in Debug.

5. There are no adjustments to be made on the Activator programmers. However, there is a calibration procedure which should be run periodically to ensure that the programmer is operating within specification. The procedure is available on Action Fax, uses standard laboratory equipment, and takes approximately 1/2 hour to run. Currently, our lab runs the calibration procedure every 6 months or after shipment of the hardware prior to programming flight parts.

6. Statistics should be kept on programming yield (at least informally). An abnormally low yield on semi-custom packaged devices led to the finding of inadequate device preparation and the need for corrective action. Normally, we have seen yields of 98% or higher.

SOCKET TIPS

The Actel 1995 Data Book recommends the Yamaichi socket for the A1280 in a CQFP172 package. However, this socket will only work on parts with date codes later than 9502. To be compatible with older parts that may still be in stock, use the Enplas OTQ-196-0.635-04, which is similar to the socket on the Activator programmer adapter.

ACT 3 EVALUATION

A joint effort by NASA (GSFC and JPL) and Aerospace Corp. is underway to evaluate the Act 3 family in the radiation environment. All testing planned will be conducted on the Actel A1460A (Matsushita die) in either a 207-pin PGA or a 196-pin QFP. The TD1460 chip, based on the TD1020 and TD1280, will be used for total dose testing with a Cobalt-60 source. The RK3, based on the TMRA1BRB and TMRA2.C (GSFC designs) and the AERO1020 and AERO1280 (Aerospace designs) will be used for SEE testing. Additionally, 5 RK3’s will be instrumented and flown in a space-borne experiment to compare on-orbit performance with predictions from ground-based testing. The A1460A consists of the equivalent of approximately 6,000 gate array gates and is a 0.8 mm part. While the A14100 10,000 gate part is more attractive for flight applications, the A1460A was furthest along on product development by Actel and was available for testing.

In the Act 3, we will be testing some new architectural features. I/O modules have edge-trigerred flip-flops, with the input registers attractive for system desigs with the 0 nS hold time specification. Also, there is a new internal high-speed clock, the HCLK. Registers are made utilizing these new features in addition to shift registers made from C-Modules, S-Modules, and a TMR string made from S-Modules. Some new features are included in this chip to improve SEE testing. The logic can directly look at combinational and clock upsets, based on clock upsets observed on the A1020x series. Also, the TMR string has been upgraded for the maximum protection against SEU’s. First, the number of voting circuits has been tripled- this ELIMINATES the overhead and speed penalty for discrete voters since the 4:1 mux which implements it is combinable with the flip-flop receiving 'corrected' data. Also, a combinational upset on a voter would be ingored since the voters themselves are all redundant. Now a TMR flip-flop consists of just 3 S-Modules for these shift registers. The other TMR improvement is that all flip-flops in a TMR triplet are on separate branches of the clock tree, making clock upsets much less likely to cause any upsets. While this scheme has the desirable features listed above, it does place a greater load on the internal routing resources. It turns out that it was fairly easy to place the three flip-flops in a triplet in very close proximity to each other and the circuit routed with no problems. Additionally, timing analysis showed that the circuits, with test logic, will operate at 40 MHz internally, at worst-case conditions.

The RK3 test chip consists of 4 different modes: Johnson twisted ring counter; direct inputs allowing any waveform to be entered; stream of 1’s, and a stream of 0’s. The 0 and 1 streams are useful for determining upset rates as a function of state, the direct input is useful for chip failure diagnostics as well as arbitrary pattern input, and the Johnson twisted ring counter is directly compatible with previous AEROxxxx designs and test equipment and gives an average upset rates for the two states.

There are 500 flip-flops in shift registers in the RK3, divided as follows:

MA1, MA2: 50 C-Modules using routed clock.
MB1, MB2: 50 S-Modules using HCLK.
MB3, MB4: 50 S-Modules using routed clock.
MC1: 50 TMR-Modules using HCLK.
I/O: 50 Input Flip-flops (IREC) using IOCLK.

Preliminary SEE testing of the RK3 A1460A has been completed. Key parameters are included in the above table and data is shown in the chart below. No latchup was detected and as with other dielectric antifuse devices, SEDR was detected with heavy ions. Also, as expected, the SEU rate increased with decreasing supply voltage although no significant difference was observed when switching between 5.0 VDC and 5.5 VDC. As had been seen on A1280A’s and more recently the RH1280, there was a SEU sensitivity to flip-flop state. The TD1460 device has been prepared and the bias board completed. A first look at the total dose performance is expected by the next edition of EEE Links.

A1460A/RK3 SEU DATA

ACKNOWLEDGEMENTS and REFERENCES

1."SEU Hardening of Field Programmable Gate Arrays for Space Applications and Device Characterization," Katz, Barto, McKerracher, Carkhuff, and Koga, IEEE Trans. on Nucl. Sci., Dec. 1984.

2.FPGA Data Book and Design Guide, 1995, Actel Corp.

3.NASA/JPL - Gary Swift.

4.Aerospace Corp. - Rocky Koga and Sue Penzin

5.Actel Corp. - Brian Cronquist and Mike Sarpa