Test Summary for the
National LVDS Line Drivers and Receivers

Test Date: February, 1997, July 1997, September 1997

Test Location: BNL, NY

Prepared By: NASA/GSFC (R. Katz, A. Feizi)

Summary Date: September 26, 1997

Devices Tested: DS90C31 (Transmitter), DS90C32 (Receiver)

DUT Description

From National Semiconductor Literature:

The DS90C31 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90C31 accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 11mW typical.

The DS90C031 and companion line receiver (DS90C32) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.

 

Some key characteristics:

+/- 350 mV differential voltage; this drastically decreases power in the load resistance.

400 pSec maximum differential skew (5V, 25° C)

3.5 nSec maximum propagation delay

pin compatible with 26C31/26C32 family - note different signalling levels though. Another key difference from RS-422 is the inability to use these devices for power switching subsystems.

typical rise/fall times of 0.35 nSec!

CMOS epi device with a p-type substrate.

Test Circuit Description

A single DUT card was used to test both the DS90C31 and the DS90C32 devices. The devices were configured in a loop of 4 transmitter-receiver pairs. The input was programmed by the test equipment and remained static over the course of the test. The output was monitored in two ways: first, the output of the loop was directly monitored by the test equipment to ensure that all of the devices were functional; second, the output of the last receiver was fed into the clock input of a 54AC109 configured in a ‘T’ flip-flop mode. This permitted the detection and counting of transient errors since this configuration eliminate the need for a high bandwith link out of the vacuum chamber. The DUT card had a controlled impedance of 100 ohms. The DUTS and terminating resistors were all surface mount devices. The basic schematic is shown in Figure 1.

 

Figure 1: DUT Circuit

 

DS90C31 Transmitter Test Results

Two devices were tested (S/N 001 and S/N 003) and were exposed to Nickel ions at various angles with LET’s ranging from 27.5 to 56.8 MeV/mg/cm2. All tests were run at VCC = 5.5VDC. A standard fluence of 107 ions/cm2 was used for all runs, except when the run was terminated because of a latchup condition. At a LET of 27.5 MeV/mg/cm2 the device latched up for 2 out of the 5 runs. Transient upsets were recorded when the device was biased with a logic ‘0’. For two runs, each with a fluence of 107 ions/cm2 and the device biased with a logic ‘1’, no upsets were seen. Upsets were seen with higher LETs but the number was contaminated by the device latching up. LVDS DS90C31 latchup data is shown in Figure 2; an ICC strip chart of a latchup is shown in Figure 3.

Discussions with the manufacturer are ongoing concerning the latchup of the transmitter device. Additional latchup tests with a second lot of parts was run in July 1997 at BNL. The results are shown in Figure 4. Note that these results have considerable variability in part to part latchup performance.

DS90C32 Receiver Test Results

Three devices were tested (S/N 001, S/N 002, and S/N 003) and were exposed to Chlorine, Nickel, and Bromine ions at various angles with LET’s ranging from 17.1 to 77.3 MeV/mg/cm2. All tests were run at either VCC = 4.5VDC or 5.5VDC. A standard fluence of 107 ions/cm2 was used for all runs. There were no latchups detected for any run. Transient upsets were recorded when the device was biased with either a logic ‘0’ or a logic ‘1’, with the logic ‘1’ state appearing slightly harder. The transient upset threshold for these devices is approximately 20 MeV/mg/cm2. LVDS DS90C32 upset data is shown in Figure 5.

 

Figure 2: LVDS Transmitter Latchup Data - First Lot of Parts

 

 

Figure 3: ICC Strip Chart of Latchup in a DS90C031

 

 

Figure 4: LVDS Transmitter Latchup Data - Second Lot of Parts

 

 

Figure 5: LVDS Receiver Upset Data

A third round of heavy ion testing has been completed. Latch up currents of approximately 30 mA were seen in each test. The following is a summary of the September, 1997 test data.

 

 

Run #

S/N

Ion

Angle

LET

Latch

Logic Upsets

Run 1

LVT1

Bromine

0

37

No

16

Run 2

LVT1

Bromine

45

52

Yes

 

Run 3

LVT1

Bromine

34.5

45

Yes

 

Run 4

LVT1

Bromine

25

42

No

8

Run 5

LVT2

Bromine

0

37

Yes

 

Run 6

LVT2

Bromine

0

37

Yes

 

Run 7

LVT3

Bromine

0

37

No

 

Run 8

LVT3

Bromine

45

52

No

22

Run 9

LVT3

Bromine

52

60

No

20